Concurrent virtual storage management

ABSTRACT

A memory system is configured for access by a plurality of computer processing units. An address lock bit is configured in a translation table of the memory system. The address lock supports both address lock shared and address lock exclusive functions. A storage manager of an operating system configured to obtain exclusive access to an entry in a DAT table either by obtaining an address space lock exclusive or obtaining an address space lock shared, and setting a lock bit in a DAT entry.

PRIORITY

This application is a continuation of and claims priority from U.S.patent application Ser. No. 14/871,265, filed on Sep. 30, 2015, entitled“CONCURRENT VIRTUAL STORAGE MANAGEMENT,” the content of which isincorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to memory management and, morespecifically, to management of concurrent access to virtual memory datastructures.

Dynamic address translation (DAT) is used in many computer architecturesto implement a mapping between a virtual address and real address. Thevirtual address represents a layer of indirection between an applicationand the underlying hardware that provides the application withabstraction of a contiguous range of storage, as well as provides morestorage than the actual amount of random access memory available in asystem configuration. Many computer architectures employ a multi-levelDAT hierarchy to implement virtual memory in order to reduce the amountof storage required for DAT tables.

SUMMARY

An embodiment includes a memory system configured for access by aplurality of computer processing units. An address lock bit isconfigured in a translation table of the memory system. The address locksupports both address lock shared and address lock exclusive functions.A storage manager of an operating system is configured to obtainexclusive access to an entry in a DAT table either by obtaining anaddress space lock exclusive or obtaining an address space lock shared,and setting a lock bit in a DAT entry.

Additional features and advantages are realized through the techniquesof the present invention. Other embodiments and aspects of the inventionare described in detail herein and are considered a part of the claimedinvention. For a better understanding of the invention with theadvantages and the features, refer to the description and to thedrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter which is regarded as the invention is particularlypointed out and distinctly claimed in the claims at the conclusion ofthe specification. The forgoing and other features, and advantages ofthe invention are apparent from the following detailed description takenin conjunction with the accompanying drawings in which:

FIG. 1A is a block diagram of a memory mapping architecture inaccordance with an embodiment;

FIG. 1B is depicts a virtual storage address translation structure thatmay be implemented using the memory mapping architecture of FIG. 1A inan embodiment;

FIG. 2A depicts a sample segment table entry in accordance with anembodiment;

FIG. 2B depicts a sample page table entry in accordance with anembodiment;

FIG. 3 depicts a flow diagram of a process for performing a pageoperation using the memory management techniques in accordance with anembodiment; and

FIG. 4 is block diagram of a system upon which memory managementtechniques may be implemented in accordance with an embodiment.

DETAILED DESCRIPTION

A memory mapping architecture may employ a multi-level hierarchy ofstorage components. As shown, e.g., in FIG. 1A, a five-level hierarchy100 of z/Architecture for IBM mainframe computers provides through ahardware control register 102, a region first table 110 in the firstlevel of the hierarchy. The region first table includes a region firstindex 112 that points to a region second table 120 in the second levelof the hierarchy. The region second table 120 includes a region secondindex 122 that points to a region third table 130 in the third level inthe hierarchy. The region third table 130 includes a region third index132 that points to a segment table 140 in the fourth level. The segmenttable 140 includes a segment table index 142 that points to a page table150 in the fifth level of the hierarchy. The page table 150 (which isthe lowest level in the hierarchy) includes a page table index 152 thatcontains a real address 160.

A virtual storage address translation structure 170 for the hierarchy100 is shown in FIG. 1B, in which RFX refers to the region first index112, RSX refers to the region second index 122, and RTX refers to theregion third index 132. In addition, SX refers to the segment tableindex 142, PX refers to the page table index 152, and BX refers to abase index. It will be understood that other memory mappingarchitectures may be employed to realize the advantages of theembodiments described herein. For example, an alternative memory mappingscheme may employ an inverted page table where a process identifier andvirtual address pair is converted to a real address, e.g., by means of ahashing scheme.

The following terminology is presented herein to provide a betterunderstanding of aspects of the embodiments.

Page fault. A page fault represents an event where an applicationaccesses a page of storage which is not backed up in a real frame. Thedata may exist in some other medium normally referred to as auxiliarystorage or it may be storage that has no data associated with it (e.g.,a first reference). In the former case, the operating system isresponsible for obtaining a frame and initiating input I/O to bring thedata into real storage and for suspending the unit of work until the I/Ohas completed. In the latter case, a frame must be obtained and cleared,and the real address of the frame must be stored in the page tableentry.

Page stealing. Page stealing is employed by the operating system whenthe number of available real frames is below some critical threshold.The operating system attempts to select frames which are unlikely to bereferenced in the near future and page them out to auxiliary storage.Once the output I/O completes, the frame is freed and the total pool ofavailable frames increases.

Page fixing. Page fixing is a way for an application program toestablish a virtual to real bind on a page of storage. When a page isfixed it is not a steal candidate and operations such as I/O thatrequire the page to remain in real storage for the duration of theoperation can be performed.

Many operating systems lock down all page level operations within anaddress space for all or parts of the entire duration of a page fault,segment fault or other events that affect DAT structures. As processesbecome more multi-threaded and computer architectures support largernumbers of CPUs, it becomes increasingly important for the operatingsystem to support concurrent page or segment operations within a singleaddress space. In IBM's z/OS operating system, such operations currentlyobtain exclusive access to an address space lock referred to as a RealStorage Manager Address (RSMAD) lock which prevents any concurrentstorage related activity to occur within an address space. Transitioningfrom a scheme of mutual exclusion to one where multiple events areprocessed concurrently can represent a major change to the operatingsystem's architecture, requiring code changes to every address spacelevel real storage management function, even the ones that are notperformance sensitive. The embodiments described herein provide atechnique for supporting intra-address space level parallelism for theperformance critical parts of address space level storage management.Embodiments also provide a means of introducing changes in a piecemealmanner so that an agile software development process can be employed.

Memory managers typically serialize their processing on the dynamicaddress translation (DAT) structures of an address space basis by usinga lock. When the lock is held, all other virtual memory relatedactivities for the address space are forced to wait for the lock ownerto free the lock before proceeding. When there are multiple threads thatare processing distinct pages within the same address space, two threadscan normally work concurrently to perform their respective functions.For example, thread 1 is taking a page fault on page A while thread 2 isattempting to page fix page B. Neither thread has any dependency on theother, other than that they share the same DAT structures. In theembodiments described herein, both threads can concurrently processtheir respective pages by obtaining shared serialization on the virtualmemory translation structures and locking the individual pages. As longas each thread locks a page that isn't already locked, the threads canperform their functions concurrently. When a thread encounters a lockedpage, it must drop shared serialization and reobtain exclusiveserialization, locking down the entire address space. The same approachmay also be taken for larger page sizes (e.g., in z/Architecture, 1 MBpages) or in the case of a segment where there is no page tableassociated with it. In this case, the locking occurs at the segmententry instead of the page table entry.

An embodiment provides concurrent virtual memory management in a systemhaving a large number of computer processing units (CPUs). Theconcurrent virtual memory management provides a scheme that allowsconcurrency for certain high performance sensitive real memory storagetasks while allowing other less performance sensitive functions to lockdown an entire address space without requiring any code modifications.

To this end, the address space lock is converted into a shared/exclusivelock. The performance sensitive real storage management functions can bechanged to obtain this lock shared and still be serialized with anyexisting functions which continue to obtain the address space lock inexclusive mode.

A function (e.g., page fault) that uses shared address space levellocking needs to have a way to serialize the page being faulted on withother units of work (e.g., another page fault on the same page from adifferent thread). A single bit is used in both the Page Table Entry(PTE), and Segment Table Entry (STE). These bits are referred to hereinas PTELock and STELock, respectively. As shown in FIG. 2A, a segmenttable entry 200 includes a field 202 for location, an invalid (I) bit204, a 1 MB page backing (FC) bit 206, and a lock (L) bit 208. Thelocation field stores the real address of the page table frame when I=0and FC=0. The location field stores the real address of a 1 MB framewhen I=0 and FC=1 (storage is mapped as a 1 MB page and backed with a 1MB frame). The location indicates an external location of a 1 MB pagewhen I=1 and FC=1. Thus, the FC bit 206 distinguishes how the memorymanagement unit of the hardware is to interpret the DAT structure. Thelock bit L may be set when FC=1 (mapped to a 1 MB page) or I=1 (segmentis invalid and does not point to a page table).

In FIG. 2B, a page table entry (PTE) 220 is shown. The page table entry220 includes a field for location 222, an invalid (I) bit 224, and alock (L) bit 226. Alternatively, if the data is in external storage(e.g., auxiliary storage), the field for location 222 may hold theaddress for the auxiliary storage. In FIG. 2B, the location is the realaddress of a page when I=0. If the data is in external storage, thelocation field 222 holds the external location in auxiliary storage. IfI=1, the page is invalid, and if L=1, the page is locked.

When the address space lock is held shared, the storage managementfunction (e.g., page fault processing) can serialize the lowest validlevel in the DAT tables mapping a virtual address by setting either thePTELock or STELock bit using a serializing instruction such as Compareand Swap in z/Architecture. If the Compare and Swap instruction fails tolock either the page or the segment, meaning that there is some otherthread which is currently processing the same page or segment, thefunction must drop the address space lock that was held shared andreobtain it exclusive. This forces the requester to wait until the unitof work that is currently processing the page or segment to completetheir processing by virtue of the fact that they hold the address spacelock shared.

Since only the lowest valid DAT structure is locked, locking the segmentis only applicable when there is no page table (i.e., when it is thelowest DAT structure in the hierarchy that maps the target virtualaddress). Once a page table real address is inserted into a lockedsegment, the STELock bit is no longer applicable since a page table mapsthe segment and other threads may lock and processes pages within thesegment. Additionally, when shared address space level serialization isin effect, a STE cannot be invalidated if it points to a page tablebecause other units of work which hold the address space lock shared mayalso be accessing the page table and may have locked pages to which thepage table maps. So if one were to view DAT structures as a tree,branches may only be added to a node holding shared address spaceserialization and locking the node, but removing branches requiresexclusive serialization.

FIG. 3 describes a process for implementing operations using theexemplary memory management techniques. FIG. 3 describes a process forperforming a page function.

In block 302, an address space level lock shared is obtained shared topartially serialize the DAT tables associated with the page. Onceobtained, the DAT tables down to the next to lowest DAT structure isguaranteed to exist. For example, if a 4 k page is being processed, thepage table will remain intact while the shared address space lock isheld, although the entries in the page table may change. Similarly, if a1 MB page is being processed, the segment table will remain intact, butthe entries may change.

At block 304, the DAT structures for the page are located, and a pagelock is initiated at block 306.

At block 308, it is determined whether the page is already locked (i.e.,whether the page lock initiation in block 306 failed). If the page lockinitiation failed, the shared address space lock is dropped at block310, and the address space lock exclusive is obtained in block 312. Thisinvolves waiting for all shared holders of the address space lock torelease the lock. The page operation is performed in block 314, and theaddress space lock is dropped in block 316.

If the unit of work successfully locked the page or segment the pageoperation can be performed. After the operation completes, the page orsegment is unlocked in block 320, and the address space lock is releasedin block 322. The page operation performed (blocks 314 and 318) mayinclude resolving a page fault, a page fix/unfix, a page steal, etc.

Segment fault processing using the exemplary memory managementtechniques is very similar to the page fault processing described inFIG. 3 above, with the exception that the segment may either be backedwith a 1 MB frame or a page table, depending on the attributes of thestorage system and the availability of 1 MB frames. In the case wherethe segment is backed by a page table, the segment is no longer thelowest level DAT structure in the DAT tree and thus the lock bit L inthe segment table entry becomes meaningless when the segment table entrypoints to a page table.

FIG. 4 depicts a block diagram of a multi-processor system 400 uponwhich the exemplary memory management functions may be implemented in anembodiment.

The system in FIG. 4 includes several execution units or core processors402, with each core processor 402 having its own dedicated high-levelcaches (L1 cache not shown, L2 cache 404, and L3 cache 406). Each coreprocessor 402 is connected, via a bus to a lower level (LL) cache 408and to an I/O controller 414. In the embodiment shown in FIG. 4, the I/Ocontroller 414 is in communication with a disk drive 416 (e.g., a harddisk drive or “HDD”, which may be an auxiliary storage location) and anetwork 418 to transmit and/or to receive data and commands. Also, thelower level cache 408 is connected to a memory controller 410 (alsoreferred to herein as storage manager). The memory controller 410operates according to the VSA structure (see, e.g., FIGS. 1A-1B).

As shown in FIG. 4, tables 425 (region, segment, and page) may reside inone or more caches, and is shown as part of one of L3 caches 406 forillustrative purposes. In an embodiment, the memory controller 410obtains a lock on a page or segment in memory. The lock obtainedcorresponds to one of the lock shared and lock exclusive functions inorder to perform a page operation.

In an embodiment, operating systems are executed on the core processors402 to coordinate and provide control of various components within thecore processors 402 including memory accesses and I/Os. Each coreprocessor 402 may operate as client or as a server. The storage managermay function through respective operating systems.

In an embodiment, instructions for an operating system, applicationand/or program are located on storage devices, such as disk drive 416,that are loaded into main memory (in the embodiment shown in FIG. 4, themain memory is implemented by DRAM 412) for execution by the coreprocessor 402. The processes performed by the core processor 402 areperformed using computer usable program code, which may be located in amemory such as, main memory (e.g., DRAM 412), LL cache 408, L2 cache 404and/or L3 cache 406. In one embodiment, the instructions are loaded intothe L2 cache 404 or the L3 cache 406 on a core processor 402 beforebeing executed by the corresponding core processor 402.

A bus is shown in FIG. 4 to connect the core processors 402 to an I/Ocontroller 414 and the LL cache 408. The bus may be comprised of aplurality of buses and may be implemented using any type ofcommunication fabric or architecture that provides for a transfer ofdata between different components or devices attached to the fabric orarchitecture. In addition, the input/output (I/O) controller 414transmits data to and receives data from, a disk drive 416 and a network418.

The multi-processor system shown in FIG. 4 may take the form of any of anumber of different data processing systems including client computingdevices, server computing devices, a tablet computer, laptop computer,telephone or other communication device, a personal digital assistant(PDA), or the like. In some illustrative embodiments, the system shownin FIG. 4 is a portable computing device that is configured with flashmemory to provide non-volatile memory for storing operating system filesand/or user-generated data, for example. In other illustrativeembodiments, the system shown in FIG. 4 is any type of digitalcommercial product that utilizes a memory system. For example, thesystem shown in FIG. 4 may be a printer, facsimile machine, flash memorydevice, wireless communication device, game system, portable video/musicplayer, or any other type of consumer electronic device. Essentially,the system shown in FIG. 4 may be any known or later developed dataprocessing system without architectural limitation.

The example memory device described herein is a DRAM 412; however, othertypes of memory may be utilized for main memory in accordance with anembodiment. For example, the main memory may be a static random accessmemory (SRAM) or a flash memory and/or it may be located on a memorymodule (e.g., a dual in-line memory module or “DIMM”) or other cardstructure. Further, as described herein, the DRAM 412 may actually beimplemented by a plurality of memory devices.

Technical effects and benefits include techniques for supportingintra-address space level parallelism for the performance critical partsof address space level storage management. Techniques also provide ameans of introducing changes in a piecemeal manner so that an agilesoftware development process can be employed.

The present invention may be a system, a method, and/or a computerprogram product. The computer program product may include a computerreadable storage medium (or media) having computer readable programinstructions thereon for causing a processor to carry out aspects of thepresent invention. The computer readable storage medium can be atangible device that can retain and store instructions for use by aninstruction execution device. The computer readable storage medium maybe, for example, but is not limited to, an electronic storage device, amagnetic storage device, an optical storage device, an electromagneticstorage device, a semiconductor storage device, or any suitablecombination of the foregoing. A non-exhaustive list of more specificexamples of the computer readable storage medium includes the following:a portable computer diskette, a hard disk, a random access memory (RAM),a read-only memory (ROM), an erasable programmable read-only memory(EPROM or Flash memory), a static random access memory (SRAM), aportable compact disc read-only memory (CD-ROM), a digital versatiledisk (DVD), a memory stick, a floppy disk, a mechanically encoded devicesuch as punch-cards or raised structures in a groove having instructionsrecorded thereon, and any suitable combination of the foregoing. Acomputer readable storage medium, as used herein, is not to be construedas being transitory signals per se, such as radio waves or other freelypropagating electromagnetic waves, electromagnetic waves propagatingthrough a waveguide or other transmission media (e.g., light pulsespassing through a fiber-optic cable), or electrical signals transmittedthrough a wire.

Computer readable program instructions described herein can bedownloaded to respective computing/processing devices from a computerreadable storage medium or to an external computer or external storagedevice via a network, for example, the Internet, a local area network, awide area network and/or a wireless network. The network may comprisecopper transmission cables, optical transmission fibers, wirelesstransmission, routers, firewalls, switches, gateway computers and/oredge servers. A network adapter card or network interface in eachcomputing/processing device receives computer readable programinstructions from the network and forwards the computer readable programinstructions for storage in a computer readable storage medium withinthe respective computing/processing device.

Computer readable program instructions for carrying out operations ofthe present invention may be assembler instructions,instruction-set-architecture (ISA) instructions, machine instructions,machine dependent instructions, microcode, firmware instructions,state-setting data, or either source code or object code written in anycombination of one or more programming languages, including an objectoriented programming language such as Smalltalk, C++ or the like, andconventional procedural programming languages, such as the “C”programming language or similar programming languages. The computerreadable program instructions may execute entirely on the user'scomputer, partly on the user's computer, as a stand-alone softwarepackage, partly on the user's computer and partly on a remote computeror entirely on the remote computer or server. In the latter scenario,the remote computer may be connected to the user's computer through anytype of network, including a local area network (LAN) or a wide areanetwork (WAN), or the connection may be made to an external computer(for example, through the Internet using an Internet Service Provider).In some embodiments, electronic circuitry including, for example,programmable logic circuitry, field-programmable gate arrays (FPGA), orprogrammable logic arrays (PLA) may execute the computer readableprogram instructions by utilizing state information of the computerreadable program instructions to personalize the electronic circuitry,in order to perform aspects of the present invention.

Aspects of the present invention are described herein with reference toflowchart illustrations and/or block diagrams of methods, apparatus(systems), and computer program products according to embodiments of theinvention. It will be understood that each block of the flowchartillustrations and/or block diagrams, and combinations of blocks in theflowchart illustrations and/or block diagrams, can be implemented bycomputer readable program instructions.

These computer readable program instructions may be provided to aprocessor of a general purpose computer, special purpose computer, orother programmable data processing apparatus to produce a machine, suchthat the instructions, which execute via the processor of the computeror other programmable data processing apparatus, create means forimplementing the functions/acts specified in the flowchart and/or blockdiagram block or blocks. These computer readable program instructionsmay also be stored in a computer readable storage medium that can directa computer, a programmable data processing apparatus, and/or otherdevices to function in a particular manner, such that the computerreadable storage medium having instructions stored therein comprises anarticle of manufacture including instructions which implement aspects ofthe function/act specified in the flowchart and/or block diagram blockor blocks.

The computer readable program instructions may also be loaded onto acomputer, other programmable data processing apparatus, or other deviceto cause a series of operational steps to be performed on the computer,other programmable apparatus or other device to produce a computerimplemented process, such that the instructions which execute on thecomputer, other programmable apparatus, or other device implement thefunctions/acts specified in the flowchart and/or block diagram block orblocks.

The flowchart and block diagrams in the Figures illustrate thearchitecture, functionality, and operation of possible implementationsof systems, methods, and computer program products according to variousembodiments of the present invention. In this regard, each block in theflowchart or block diagrams may represent a module, segment, or portionof instructions, which comprises one or more executable instructions forimplementing the specified logical function(s). In some alternativeimplementations, the functions noted in the block may occur out of theorder noted in the figures. For example, two blocks shown in successionmay, in fact, be executed substantially concurrently, or the blocks maysometimes be executed in the reverse order, depending upon thefunctionality involved. It will also be noted that each block of theblock diagrams and/or flowchart illustration, and combinations of blocksin the block diagrams and/or flowchart illustration, can be implementedby special purpose hardware-based systems that perform the specifiedfunctions or acts or carry out combinations of special purpose hardwareand computer instructions.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of onemore other features, integers, steps, operations, element components,and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of allmeans or step plus function elements in the claims below are intended toinclude any structure, material, or act for performing the function incombination with other claimed elements as specifically claimed. Thedescription of the present invention has been presented for purposes ofillustration and description, but is not intended to be exhaustive orlimited to the invention in the form disclosed. Many modifications andvariations will be apparent to those of ordinary skill in the artwithout departing from the scope and spirit of the invention. Theembodiment was chosen and described in order to best explain theprinciples of the invention and the practical application, and to enableothers of ordinary skill in the art to understand the invention forvarious embodiments with various modifications as are suited to theparticular use contemplated.

What is claimed is:
 1. A system, comprising: a memory system configuredfor access by a plurality of computer processing units; a lock bitconfigured in a dynamic address translation (DAT) table of the memorysystem, the lock bit supporting a first function comprising obtaining anaddress lock shared on a DAT structure represented in the DAT table anda second function comprising obtaining an address lock exclusive on theDAT structure, wherein the memory system is organized according to amulti-level hierarchy, and wherein a region table corresponds to ahigher level in the multi-level hierarchy than a segment table and thesegment table corresponds to a higher level in the multi-level hierarchythan a page table; and a storage manager of an operating system, thestorage manager configured to: determine that the DAT structure is aparticular segment table in the memory system, determine that theparticular segment table is the lowest valid level in the DAT tablemapping a virtual address based at least in part on determining that theparticular segment table does not point to a page table, initiate theaddress lock shared on the particular segment table at least in part byserializing, via a serialization instruction issued by a storagemanagement function, the lowest valid level in the DAT table mapping thevirtual address by attempting to set the lock bit, wherein a segmenttable entry in the DAT table comprises the lock bit, the segment tableentry corresponding to the particular segment table, determine thatsetting the lock bit failed, determine that the particular segment tableis already locked based at least in part on determining that setting thelock bit failed, drop the address space lock shared on the particularsegment table, and obtain the address space lock exclusive on theparticular segment table prior to performing a corresponding task by acomputer processing unit.
 2. The system of claim 1, wherein the storagemanager is further configured to release the address space lockexclusive subsequent to the corresponding task being performed by thecomputer processing unit.
 3. The system of claim 2, wherein thecorresponding task is a first task, and wherein the storage manager isfurther configured to: obtain the address space lock shared on theparticular segment table subsequent to release of the address space lockexclusive at least in part by setting the lock bit, and release theaddress space lock shared to unlock the particular segment tablesubsequent to a second task being performed by the computer processingunit.
 4. The system of claim 1, wherein the corresponding task is asegment fault.
 5. A method, comprising: configuring a lock bit in adynamic address translation (DAT) table of a memory system to support afirst function comprising obtaining an address lock shared on a DATstructure represented in the DAT table and a second function comprisingobtaining an address lock exclusive on the DAT structure, wherein thememory system is configured for access by a plurality of computerprocessing units, and wherein the memory system is organized accordingto a multi-level hierarchy, and wherein a region table corresponds to ahigher level in the multi-level hierarchy than a segment table and thesegment table corresponds to a higher level in the multi-level hierarchythan a page table, and by a storage manager of an operating systemexecuting on the memory system: determining that the DAT structure is aparticular segment table in the memory system, determining, by thestorage manager, that the particular segment table is the lowest validlevel in the DAT table mapping a virtual address based at least in parton determining that the particular segment table does not point to apage table, initiating, by the storage manager the address space lockshared on the particular segment table at least in part by serializing,via a serialization instruction issued by a storage management function,the lowest valid level in the DAT table mapping the virtual address byattempting to set the lock bit, wherein a segment table entry in the DATtable comprises the lock bit, the segment table entry corresponding tothe particular segment table, determining that setting the lock bitfailed, determining that the particular segment table is already lockedbased at least in part on determining that setting the lock bit failed,dropping the address space lock shared on the particular segment table,and obtaining the address space lock exclusive on the particular segmenttable prior to performing a corresponding task by a computer processingunit.
 6. The method of claim 5, further comprising releasing, by thestorage manager, the address space lock exclusive subsequent to thecorresponding task being performed by the computer processing unit. 7.The method of claim 5, wherein the task is a first task, the methodfurther comprising by the storage manager: obtain the address space lockshared on the particular segment table subsequent to release of theaddress space lock exclusive at least in part by setting the lock bit,and releasing the address space lock shared to unlock the particularsegment table subsequent to a second task being performed by thecomputer processing unit.
 8. The method of claim 5, wherein thecorresponding task is a segment fault.
 9. A computer program productcomprising a computer readable storage medium having programinstructions embodied therewith, the program instructions executable bya processor to cause the processor to perform: configuring a lock bit ina dynamic address translation (DAT) table of a memory system to supporta first function comprising obtaining an address lock shared on a DATstructure represented in the DAT table and a second function comprisingobtaining an address lock exclusive on the DAT structure, wherein thememory system is configured for access by a plurality of computerprocessing units, and wherein the memory system is organized accordingto a multi-level hierarchy, and wherein a region table corresponds to ahigher level in the multi-level hierarchy than a segment table and thesegment table corresponds to a higher level in the multi-level hierarchythan a page table, and by a storage manager of an operating systemexecuting on the memory system: determining that the DAT structure is aparticular segment table in the memory system, determining, by thestorage manager, that the particular segment table is the lowest validlevel in the DAT table mapping a virtual address based at least in parton determining that the particular segment table does not point to apage table, initiating, by the storage manager the address space lockshared on the particular segment table at least in part by serializing,via a serialization instruction issued by a storage management function,the lowest valid level in the DAT table mapping the virtual address byattempting to set the lock bit, wherein a segment table entry in the DATtable comprises the lock bit, the segment table entry corresponding tothe particular segment table, determining that setting the lock bitfailed, determining that the particular segment table is already lockedbased at least in part on determining that setting the lock bit failed,dropping the address space lock shared on the particular segment table,and obtaining the address space lock exclusive on the particular segmenttable prior to performing a corresponding task by a computer processingunit.
 10. The computer program product of claim 9, further comprisingreleasing, by the storage manager, the address space lock exclusivesubsequent to the corresponding task being performed by the computerprocessing unit.